The present invention relates to a semiconductor integrated circuit, and more particularly, to a high-speed semiconductor integrated circuit.
Conventionally, the speed of a semiconductor integrated circuit, particularly a flip-flop circuit, is increased by incorporating a dynamic circuit into its internal structure as described in, for example, JP No. 2003-060497 A. The dynamic flip-flop circuit described in this publication receives a plurality of pieces of data, selects any one of them, and holds and outputs the selected data.
Hereinafter, the structure of the flip-flop circuit having the data selection function will be described with reference to FIG. 3A. In FIG. 3A, a data selection circuit 91 is provided at the previous stage of a holding circuit 90. In the data selection circuit 91, when a clock CLK is at a Low level (Low period), a node N1 is precharged to a power source potential Vdd by a p-type transistor Tr1, while a node N2 is precharged to the power source potential Vdd by a p-type transistor Tr50. Near the end of this period, one of selection signals S0 to S2 which is used to select a corresponding one of a plurality of pieces of data D0 to D2 is turned High. Subsequently, when the clock CLK goes to High and the selected data (e.g., D0) is at a High level, the electric charge of the node N1 is discharged via an n-type transistor Tr2, so that the potential of the node N1 becomes equal to that of the ground. Therefore, an n-type transistor Tr51 is turned OFF, so that the precharge potential of the node N2 is held. In this case, this potential is held as an H value by the holding circuit 90, which in turn outputs an output signal Q indicating the H value.
On the other hand, when the selected data D0 is at a Low level, the electric charge of the node N1 is not discharged, so that the potential of the Node N1 is held as it is the precharge potential and the n-type transistor Tr51 is turned ON. As a result, the electric charge of the node N2 is discharged via the n-type transistor Tr51 and the n-type transistor Tr2, so that the potential of the node N2 becomes an L value. The L value is held by the holding circuit 90, which in turn outputs an output signal Q indicating the L value.
Note that, in FIG. 3A, SI indicates a data input when scanning is performed, SE indicates a scan shift control signal, and SEB indicates an inverted signal of the scan shift control signal.
However, it was found that the conventional dynamic flip-flop circuit having the data selection function malfunctions when none of the plurality of pieces of data is selected. Hereinafter, the malfunction will be described.
In an ordinary operation, for example, the node N2 is at the precharge potential (H value) and the holding circuit 90 outputs the output signal Q indicating the H value. In this case, when none of the plurality of pieces of data D0 to D2 is selected during the next High period of the clock CLK (i.e., all the selection signals S0 to S2 have the Low value), the n-type transistor Tr2 is turned ON. However, the precharge potential of the node N1 is held, so that the n-type transistor Tr51 is turned ON. Therefore, the electric charge of the node N2 is discharged via the n-type transistors Tr51 and Tr2 to the L value. As a result, the holding circuit 90 erroneously outputs an output signal Q indicating the L value.
To solve the above-described problems, for example, the following circuit is considered which inputs a signal to the gate of the n-type transistor Tr2 as shown in FIG. 3B. Specifically, a static circuit comprising a circuit 92 including an OR circuit which receives all the selection signals S0 to S2 and a latch circuit which latches an output of the OR circuit during a High period of the clock CLK, and an AND circuit 93 which receives an output of the latch circuit and the clock CLK, is additionally provided, and an output of the AND circuit 93 is input to the gate of the n-type transistor Tr2.
In this case, however, all the selection signals S0 to S2 need to be passed through the OR circuit and the latch circuit by a rising time of the clock CLK. Therefore, an extra setup time (a time required for the static circuit to establish its output by a rising time of the clock CLK) is required, resulting in impairment of the speed of operation.